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1. general description the ptn3360d is a high-speed level shifter device which converts four lanes of low-swing ac-coupled differential input signals to dvi v1.0 and hdmi v1.4b compliant open-drain current-steering differential output signals, up to 3.0 gbit/s per lane to support 36-bit deep color mode, 4k ? 2k video format or 3d video data transport. each of these lanes provides a level-shifting differential buffer to translate from low-swing ac-coupled differential signaling on the source side, to tmds-type dc-coupled differential current-mode signaling terminated into 50 ? to 3.3 v on the sink side. additionally, the ptn3360d provides a single-ended active buffe r for voltage translation of the hpd signal from 5 v on the sink side to 3.3 v on the so urce side and provides a channel with active buffering and level shifting of the ddc channel (consisting of a clock and a data line) between 3.3 v source-side and 5 v sink-sid e. the ddc channel is implemented using active i 2 c-bus buffer technology providing capaciti ve isolation, redriving and level shifting as well as disablement (isolation between so urce and sink) of the clock and data lines. the low-swing ac-coupled differential input signals to the ptn3360d typically come from a display source with multi-mo de i/o, which supports multiple display standards, for example, displayport, hdmi and dvi. while the input differential signals are configured to carry dvi or hdmi coded data, they do not comply with the electrical requirements of the dvi v1.0 or hdmi v1.4b specif ication. by using ptn3360d, chip set vendors are able to implement such reconfigurable i/os on mult i-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set i/o pins low. see figure 1 . the ptn3360d main high-speed differentia l lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of displayport standard v1.2 and/or pci express standard v1.1 , and open-drain current-steering differential outputs compliant to dvi v1.0 and hdmi v1.4b electrical specifications. the i 2 c-bus channel actively buffers as well as level-translates the ddc signals for optimal capacitive isolation. the ptn3360d also supports power-saving modes in order to minimize current consumption when no display is active or connected. the ptn3360d is a fully featured hdmi as well as dvi level shifter. the ptn3360d supersedes ptn3360b, and provides a better high speed performance with a programmable equalizer. ptn3360d is powered from a single 3.3 v power supply consuming a small amount of power (230 mw typical) and is offered in a 48-terminal hvqfn48 package. ptn3360d enhanced performance hdmi/dvi level shifter with active ddc buffer, supporting 3 gbit/s operation rev. 4 ? 29 june 2012 product data sheet
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 2 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation remark: tmds clock and data lanes can be assigned ar bitrarily and interchangeably to d[4:1]. fig 1. typical application system diagram 002aaf240 out_d1? out_d1+ in_d1? in_d1+ hpd_source hpd_sink scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2? out_d2+ in_d2? in_d2+ out_d3? out_d3+ in_d3? in_d3+ out_d4? out_d4+ in_d4? in_d4+ ptn3360d oe_n dvi/hdmi connector 5 v 5 v 0 v to 5 v 0 v to 3.3 v 3.3 v 3.3 v 3.3 v ac-coupled differential pair clock clock lane data lane data lane data lane ac-coupled differential pair tmds data ac-coupled differential pair tmds data ac-coupled differential pair tmds data tx tx ff tmds clock pattern multi-mode display source tx tx ff tmds coded data tx tx ff tmds coded data tx tx ff tmds coded data pcie phy electrical configuration ddc i/o (i 2 c-bus) pcie output buffer reconfigurable i/os pcie output buffer pcie output buffer pcie output buffer eq5 quinary input
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 3 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 2. features and benefits 2.1 high-speed tmds level shifting ? converts four lanes of low-swing ac-coupled differential input signals to dvi v1.0 and hdmi v1.4b compliant open-drain current-steering differential output signals ? tmds level shifting operation up to 3.0 gbit/s per lane (300 mhz character clock) supporting 4k u 2k and 3d video formats ? programmable equalizer ? integrated 50 : termination resistors for self -biasing differential inputs ? back-current safe outputs to disallow current when device power is off and monitor is on ? disable feature to turn off tmds inputs and outputs and to enter low-power state 2.2 ddc level shifting ? integrated ddc buffering and level shifting (3.3 v source to 5 v sink side) ? rise time accelerator on sink-side ddc ports ? 0hz to 400khz i 2 c-bus clock frequency ? back-power safe sink-side term inals to disallow backdrive cu rrent when power is off or when ddc is not enabled 2.3 hpd level shifting ? hpd non-inverting level shift from 0 v on the sink side to 0 v on the source side, or from 5 v on the sink side to 3.3 v on the source side ? integrated 200 k : pull-down resistor on hpd sink input guarantees ?input low? when no display is plugged in ? back-power safe design on hpd_sink to disallow backdr ive current when power is off 2.4 general ? power supply 3.0 v to 3.6 v ? esd resilience to 6 kv hbm, 1 kv cdm ? power-saving modes (using output enable) ? back-current-safe design on all sink-s ide main link, ddc and hpd terminals ? transparent operation: no re-timing or software configuration required ? 48-terminal hvqfn48 package 3. applications ? pc motherboard/graphics card ? docking station ? displayport to hdmi adapters supporting 4k u 2k and 3d video formats ? displayport to dvi adapters required to drive long cables
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 4 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 4. ordering information 5. functional diagram table 1. ordering information type number topside mark package name description version PTN3360DBS PTN3360DBS hvqfn48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 ? 7 ? 0.85 mm sot619-1 fig 2. functional diagram of ptn3360d 002aaf241 out_d1? out_d1+ input bias 50 50 in_d1? in_d1+ hpd level shifter hpd_source (0 v to 3.3 v) hpd_sink (0 v to 5 v) 200 k scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2? out_d2+ in_d2? in_d2+ out_d3? out_d3+ in_d3? in_d3+ out_d4? out_d4+ in_d4? in_d4+ ptn3360d oe_n enable enable enable enable input bias 50 50 input bias 50 50 input bias 50 50 enable enable enable enable ddc buffer and level shifter eq eq5 eq eq eq
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 5 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 6. pinning information 6.1 pinning hvqfn48 package supply ground is connected to both gnd pins and exposed center pad. gnd pins and the exposed center pad must be connected to supply ground for proper device operation. for enhanced thermal, electrical, a nd board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. fig 3. pin configuration for hvqfn48 out_d4+ out_d4? v dd out_d3+ out_d3? gnd out_d2+ out_d2? v dd out_d1+ out_d1? gnd oe_n v dd gnd scl_sink sda_sink hpd_sink gnd ddc_en v dd n.c. n.c. gnd v dd gnd n.c. scl_source sda_source hpd_source rext gnd n.c. eq5 v dd gnd in_d4+ in_d4? v dd in_d3+ in_d3? gnd in_d2+ in_d2? v dd in_d1+ in_d1? gnd 002aaf242 PTN3360DBS 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 6 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 6.2 pin description table 2. pin description symbol pin type description oe_n, in_dx and out_dx signals oe_n 25 3.3 v low-voltage cmos single-ended input output enable and power saving function for high-speed differential level shifter path. when oe_n = high: in_dx termination = high-impedance out_dx outputs = high-impedance; zero output current when oe_n = low: in_dx termination = 50 ? out_dx outputs = active in_d4+ 48 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d4+ makes a differential pair with in_d4 ? . the input to this pin must be ac coupled externally. in_d4? 47 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d4 ? makes a differential pair with in_d4+. the input to this pin must be ac coupled externally. in_d3+ 45 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d3+ makes a differential pair with in_d3 ? . the input to this pin must be ac coupled externally. in_d3? 44 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d3 ? makes a differential pair with in_d3+. the input to this pin must be ac coupled externally. in_d2+ 42 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d2+ makes a differential pair with in_d2 ? . the input to this pin must be ac coupled externally. in_d2? 41 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d2 ? makes a differential pair with in_d2+. the input to this pin must be ac coupled externally. in_d1+ 39 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d1+ makes a differential pair with in_d1 ? . the input to this pin must be ac coupled externally.
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 7 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation in_d1 ? 38 self-biasing differential input low-swing differential input from display source with pci express electrical signaling. in_d1 ? makes a differential pair with in_d1+. the input to this pin must be ac coupled externally. out_d4+ 13 tmds differential output hdmi compliant tmds output. out_d4+ makes a differential pair with out_d4 ? . out_d4+ is in phase with in_d4+. out_d4 ? 14 tmds differential output hdmi compliant tmds output. out_d4 ? makes a differential pair with out_d4+. out_d4 ? is in phase with in_d4 ? . out_d3+ 16 tmds differential output hdmi compliant tmds output. out_d3+ makes a differential pair with out_d3 ? . out_d3+ is in phase with in_d3+. out_d3 ? 17 tmds differential output hdmi compliant tmds output. out_d3 ? makes a differential pair with out_d3+. out_d3 ? is in phase with in_d3 ? . out_d2+ 19 tmds differential output hdmi compliant tmds output. out_d2+ makes a differential pair with out_d2 ? . out_d2+ is in phase with in_d2+. out_d2 ? 20 tmds differential output hdmi compliant tmds output. out_d2 ? makes a differential pair with out_d2+. out_d2 ? is in phase with in_d2 ? . out_d1+ 22 tmds differential output hdmi compliant tmds output. out_d1+ makes a differential pair with out_d1 ? . out_d1+ is in phase with in_d1+. out_d1 ? 23 tmds differential output hdmi compliant tmds output. out_d1 ? makes a differential pair with out_d1+. out_d1 ? is in phase with in_d1 ? . hpd and ddc signals hpd_sink 30 5 v cmos single-ended input 0 v to 5 v (nominal) input signal. this signal comes from the dvi or hdmi sink. a high value indicates that the sink is connected; a low value indicates that the sink is disconnected. hpd_sink is pulled down by an integrated 200 k ? pull-down resistor. hpd_ source 7 3.3 v cmos single-ended output 0 v to 3.3 v (nominal) output signal. this is level-shifted version of the hpd_sink signal. scl_source 9 single-ended 3.3 v open-drain ddc i/o 3.3 v source-side ddc clock i/o. pulled up by external termination to 3.3 v. 5 v tolerant i/o. sda_source 8 single-ended 3.3 v open-drain ddc i/o 3.3 v source-side ddc data i/o. pulled up by external termination to 3.3 v. 5 v tolerant i/o. scl_sink 28 single-ended 5 v open-drain ddc i/o 5 v sink-side ddc clock i/o. pulled up by external termination to 5 v. provides rise time acceleration for low-to-high transitions. sda_sink 29 single-ended 5 v open-drain ddc i/o 5 v sink-side ddc data i/o. pulled up by external termination to 5 v. provides rise time acceleration for low-to-high transitions. table 2. pin description ?continued symbol pin type description
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 8 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation [1] hvqfn48 package supply ground is c onnected to both gnd pins and exposed center pad. gnd pins and the exposed center pad must be connected to s upply ground for proper device operation. for enhanced thermal, electrical, and board level performance, t he exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. ddc_en 32 3.3 v cmos input enables the ddc buffer and level shifter. when ddc_en = low, buffer/level shifter is disabled. when ddc_en = high, buffer and level shifter are enabled. supply and ground v dd 2, 11, 15, 21, 26, 33, 40, 46 3.3 v dc supply supply voltage; 3.3 v ? 10 %. gnd [1] 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 ground supply ground. all gnd pins must be connected to ground for proper operation. feature control signals rext 6 analog i/o current sense port used to provide an accurate current reference for the differential outputs out_dx. for best output voltage swing accuracy, use of a 10 k ? resistor (1 % tolerance) from this terminal to gnd is recommended. may also be tied to either v dd or gnd directly (0 ? ). see section 7.2 for details. n.c. 4, 10, 34, 35 - not connected eq5 3 3.3 v low-voltage cmos quinary input equalizer setting input pin. this pin can be board-strapped to one of five decode values: short to gnd, resistor to gnd, open-circuit, resistor to v dd , short to v dd . see table 4 for truth table. table 2. pin description ?continued symbol pin type description
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 9 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 7. functional description refer to figure 2 ? functional diagram of ptn3360d ? . the ptn3360d level shifts four lanes of low-s wing ac-coupled differential input signals to dvi and hdmi compliant open-drain current-steer ing differential output signals, up to 3.0 gbit/s per lane to support 36-bit deep color mode. it has integrated 50 ? termination resistors for ac-coupled differential input signals. an enable signal oe_n can be used to turn off the tmds inputs and outputs, ther eby minimizing power consumption. the tmds outputs are back-power safe to disallow current flow from a powered sink while the ptn3360d is unpowered. the ptn3360d's ddc channel provides active level shifting and buffering, allowing 3.3 v source-side termination and 5 v sink-side termination. the sink-side ddc ports are equipped with a rise time accelerator enab ling drive of long cables or high bus capacitance. this enables the system designer to isolate bus capacitance to meet/exceed hdmi ddc specification. the ptn3360d offe rs back-power safe sink-side i/os to disallow backdrive current from the ddc clock and data lines when power is off or when ddc is not enabled. an enable signal dcc_ en enables the ddc level shifter block. the ptn3360d also provides voltage transl ation for the hot plug detect (hpd) signal from 0 v to 5 v on the sink side to 0 v to 3.3 v on the source side. the ptn3360d does not re-time any data. it contains no state machines. no inputs or outputs of the device are latched or cl ocked. because the ptn3360d acts as a transparent level shifter, no reset is required. 7.1 enable and disable features ptn3360d offers different ways to enable or disable functionality, using the output enable (oe_n), and ddc enable (ddc_en ) inputs. whenever the ptn3360d is disabled, the device will be in standby m ode and power consumption will be minimal; otherwise the ptn3360d will be in active mode and power consumption will be nominal. these two inputs each affect the operation of ptn3360d differently: oe_n controls the tmds channels, ddc_en affects only the ddc channel, and hpd_si nk does not affect either of the channels. the following sections and truth table describe their detailed operation. 7.1.1 hot plug detect the hpd channel of ptn3360d functions as a le vel-shifting buffer to pass the hpd logic signal from the display sink device (via inpu t hpd_sink) on to the display source device (via output hpd_source). the output logic state of hpd_source output always follows the logic state of input hpd_sink, regardless of whether the device is in active mode or standby mode.
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 10 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 7.1.2 output enable function (oe_n) when input oe_n is asserted (active low), the in_dx and out_dx signals are fully functional. input termination resistors are enabled and the internal bias circuits are turned on. when oe_n is de-asserted (inactive high), the out_dx outputs are in a high-impedance state and drive zero output cu rrent. the in_dx input buffers are disabled and in_dx termination is disabled . power consumption is minimized. remark: note that oe_n signal level has no influence on the hpd_sink input, hpd_source output, or the scl and sda level shifters. a transition from high to low at oe_n may disable the ddc channel for up to 20 ? s. 7.1.3 ddc channel enable function (ddc_en) the ddc_en pin is active high and can be used to isolate a badly behaved slave. when ddc_en is low, the ddc channel is turned off. the ddc_en input should never change state during an i 2 c-bus operation. note that disabling ddc_en during a bus operation may hang the bus, while enabling ddc_en during bus traffic would corrupt the i 2 c-bus operation. hence, ddc_en should only be toggled while the bus is idle. (see i 2 c-bus specification).
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 11 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 7.1.4 enable/disable truth table [1] a high level on input oe_n disables only the tmds channels. a transition from high to low at oe_n may disable the ddc channe l for up to 20 ? s. [2] a low level on input ddc_en disables only the ddc channel. [3] out_dx channels ?enabled? means outputs out_dx toggling in accordance with in_dx differential input voltage switching. [4] ddc channel ?enabled? means sda_sink is connected to sda_source and scl_sink is connected to scl_source. [5] the hpd_source output logic state always follows the hpd_sink input logic state. table 3. hpd_sink, oe_n and ddc_en enabling truth table inputs channels mode hpd_sink oe_n [1] ddc_en [2] in_dx out_dx [3] ddc [4] hpd_source [5] low low low 50 ? termination to v rx(bias) enabled high-impedance low active; ddc disabled low low high 50 ? termination to v rx(bias) enabled sda_sink connected to sda_source and scl_sink connected to scl_source low active; ddc enabled low high low high-impedance high-impedance; zero output current high-impedance low standby low high high high-impedance high-impedance; zero output current sda_sink connected to sda_source and scl_sink connected to scl_source low standby; ddc enabled high low low 50 ? termination to v rx(bias) enabled high-impedance high active; ddc disabled high low high 50 ? termination to v rx(bias) enabled sda_sink connected to sda_source and scl_sink connected to scl_source high active; ddc enabled high high low high-impedance high-impedance; zero output current high-impedance high standby high high high high-impedance high-impedance; zero output current sda_sink connected to sda_source and scl_sink connected to scl_source high standby; ddc enabled
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 12 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 7.2 analog current reference the rext pin (pin 6) is an analog current sense port used to provide an accurate current reference for the differential outputs out_dx. for best output voltage swing accuracy, use of a 10 k ? resistor (1 % tolerance) connect ed between this terminal and gnd is recommended. if an external 10 k ?? 1 % resistor is not used, this pi n can be connected to gnd or v dd directly (0 ? ). in any of these cases, the output will function normally but at reduced accuracy over voltage and temperature of the following parameters: output levels (v ol ), differential output voltage swing, and rise and fall time accuracy. 7.3 equalizer the ptn3360d supports 5 level equalization setting by the quinary input pin eq5. 7.4 backdrive current protection the ptn3360d is designed for backdrive pr evention on all sink-side tmds outputs, sink-side ddc i/os and the hpd_sink input. this supports user scenarios where the display is connected and powered, but the pt n3360d is unpowered. in these cases, the ptn3360d will sink no more than a negligible amount of leakage current, and will block the display (sink) termination network from driving the power supply of the ptn3360d or that of the inactive dvi or hdmi source. 7.5 active ddc buf fer with rise time accelerator the ptn3360d ddc channel, besides providing 3.3 v to 5 v level shifting, includes active buffering and rise time acceleration wh ich allows up to 18 meters bus extension for reliable ddc applications. while retaining a ll the operating modes and features of the i 2 c-bus system during the level shifts, it permits extension of the i 2 c-bus by providing bidirectional buffering for both the data (sda) and the clock (scl) line as well as the rise time accelerator on the sink-side port (scl_sink and sda_sink) enabling the bus to drive a load up to 1400 pf or distance of 18 m on the sink-side port, and 400 pf on the source-side port (scl_source and sca_so urce). using the ptn3360d for dvi or hdmi level shifting enables the system designer to isolate bus capacitance to meet/exceed hdmi ddc specific ation. the sda and scl pins are overvoltage tolerant and are high-impedance when the ptn3360d is unpowered or when ddc_en is low. table 4. equalizer settings inputs quinary notation equalizer mode eq5 short to gnd 0 5 0db 10 k ? resistor to gnd 1 5 2db open-circuit 2 5 3.5 db 10 k ? resistor to v dd 3 5 9db short to v dd 4 5 7db
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 13 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation ptn3360d has rise time accelerators on the sink-side port (scl_sink and sda_sink) only. during positive bus transitions on the sink-side port, a current source is switched on to quickly slew the scl_sink and sda_ sink lines high once the 5 v ddc bus v il threshold level of around 1.5 v is exceeded, and turns off as the 5 v ddc bus v ih threshold voltage of approximately 3.5 v is approached. 8. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged device model: ansi/eos/esd-s5.3-1-1999, stand ard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 9. recommended operating conditions [1] input signals to these pins must be ac-coupled. [2] operation without external reference resistor is possible but will result in reduced output voltage swing accuracy. for details, see section 7.2 . 9.1 current consumption table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +4.6 v v i input voltage 3.3 v cmos inputs ? 0.3 v dd +0.5 v 5.0 v cmos inputs ? 0.3 6.0 v t stg storage temperature ? 65 +150 ?c v esd electrostatic discharge voltage hbm [1] - 6000 v cdm [2] - 1000 v table 6. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage 3.3 v cmos inputs 0 - 3.6 v 5.0 v cmos inputs 0 - 5.5 v v i(av) average input voltage in_dn+, in_dn ? inputs [1] -0 -v r ref(ext) external reference resistance connected between pin rext (pin 6) and gnd [2] -10 ? 1% - k ? t amb ambient temperature operating in free air ? 40 - +85 ?c table 7. current consumption symbol parameter conditions min typ max unit i dd supply current oe_n = 0; active mode - 70 100 ma oe_n = 1 and ddc_en = 0; standby mode --5ma
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 14 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 10. characteristics 10.1 differential inputs [1] ui (unit interval) = t bit (bit time). [2] ui is determined by the display mode. nominal bit rate ranges from 250 mbit/s to 3.0 gbit/s per lane. [3] v rx_diffp-p = 2 ?? v rx_d+ ? v rx_d ? ? . applies to in_dx signals. [4] v i(cm)m(ac) = ? v rx_d+ +v rx_d ? ? /2? v rx(cm) . v rx(cm) = dc (avg) of ? v rx_d+ +v rx_d ? ? /2. [5] differential inputs will switch to a high-impedance state when oe_n is high. 10.2 differential outputs the level shifter?s differential outputs are designed to meet hdmi version 1.4a and dvi version 1.0 specifications. [1] v tt is the dc termination voltage in the hdmi or dvi sink. v tt is nominally 3.3 v. [2] the open-drain output pulls down from v tt . [3] swing down from tmds termination voltage (3.3 v ? 10 %). table 8. differential input characteristics for in_dx signals symbol parameter conditions min typ max unit ui unit interval [1] [2] 333 - 4000 ps v rx_diffp-p differential input peak-to-peak voltage [3] 0.175 - 1.200 v t rx_eye receiver eye time minimum eye width at in_dx input pair 0.8 - - ui v i(cm)m(ac) peak common-mode input voltage (ac) includes all frequencies above 30 khz [4] --100mv z rx_dc dc input impedance 40 50 60 ? v rx(bias) bias receiver voltage 1.0 1.2 1.4 v z i(se) single-ended input impedance inputs in high-impedance state [5] 100 - - k ? table 9. differential output char acteristics for out_dx signals symbol parameter conditions min typ max unit v oh(se) single-ended high-level output voltage [1] v tt ? 0.01 v tt v tt +0.01 v v ol(se) single-ended low-level output voltage [2] v tt ? 0.60 v tt ? 0.50 v tt ? 0.40 v ? v o(se) single-ended output voltage variation logic 1 and logic 0 state applied respectively to differential inputs in_dn; r ref(ext) connected; see ta b l e 6 [3] 400 500 600 mv i oz off-state output current single-ended - - 10 ? a t r rise time 20 % to 80 % 75 - 240 ps t f fall time 80 % to 20 % 75 - 240 ps t sk skew time intra-pair [4] --1 0p s inter-pair [5] --2 5 0p s t jit(add) added jitter time jitter contribution [6] -1 0- p s
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 15 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation [4] this differential skew budget is in addition to the skew presented between in_d+ and in_d ? paired input pins. [5] this lane-to-lane skew budget is in additi on to skew between differential input pairs. [6] jitter budget for differential signals as they pass through the level shifter. 10.3 hpd_sink input, hpd_source output [1] low-speed input changes state on cable plug/unplug. [2] time from hpd_sink changing state to hpd_source changing state. includes hpd_source rise/fall time. [3] time required to transition from v oh to v ol or from v ol to v oh . [4] guarantees hpd_sink is low when no display is plugged in. 10.4 oe_n, ddc_en inputs [1] measured with input at v ih maximum and v il minimum. table 10. hpd characteristics symbol parameter conditions min typ max unit v ih high-level input voltage hpd_sink [1] 2.0 5.0 5.3 v v il low-level input voltage hpd_sink 0 - 0.8 v i li input leakage current hpd_sink - - 15 ? a v oh high-level output voltage hpd_source 2.5 - v dd v v ol low-level output voltage hpd_source 0 - 0.2 v t pd propagation delay from hpd_sink to hpd_source; 50 % to 50 % [2] --200ns t t transition time hpd_source rise/fall; 10 % to 90 % [3] 1 - 20 ns r pd pull-down resistance hpd_sink input pull-down resistor [4] 100 200 300 k ? table 11. oe_n, ddc_en input characteristics symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 - v v il low-level input voltage - 0.8 v i li input leakage current oe_n pin [1] --10 ? a
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 16 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 10.5 ddc characteristics [1] v cc1 is the pull-up voltage for ddc source. [2] v cc2 is the pull-up voltage for ddc sink. table 12. ddc characteristics symbol parameter conditions min typ max unit input and output scl_ source and sda_source, v cc1 = 3.0 v to 3.6 v [1] v ih high-level input voltage 0.7v cc1 -3.6 v v il low-level input voltage ? 0.5 - +0.3v cc1 v v ilc contention low-level input voltage ? 0.5 0.4 - v i li input leakage current v i =3.6v - - 10 ? a i il low-level input current v i =0.2v - - 10 ? a v ol low-level output voltage i ol =100 ? a or 6 ma 0.47 0.52 0.6 v v ol ? v ilc difference between low-level output and low-level input voltage contention guaranteed by design - - 70 mv c io input/output capacitance v i =3v or 0v; v dd =3.3v - 6 7 pf v i = 3 v or 0 v; v dd =0v - 6 7 pf input and output sda_ sink and scl_sink, v cc2 =4.5v to 5.5v [2] v ih high-level input voltage 0.7v cc2 -5.5 v v il low-level input voltage ? 0.5 - +1.5 v i li input leakage current v i =5.5v - - 10 ? a i il low-level input current v i =0.2v - - 10 ? a v ol low-level output voltage i ol =6ma - 0.1 0.2 v c io input/output capacitance v i =3v or 0v; v dd =3.3v - - 7 pf v i = 3 v or 0 v; v dd =0v - 6 7 pf i trt(pu) transient boosted pull-up current v cc2 =4.5v; slew rate = 1.25 v/ ? s -6-ma
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 17 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 11. package outline fig 4. package outline sot619-1 (hvqfn48) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 7.1 6.9 d h 5.25 4.95 y 1 7.1 6.9 5.25 4.95 e 1 5.5 e 2 5.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot619-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot619-1 hvqfn48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 13 24 48 37 36 25 12 1 x d e c b a e 2 01-08-08 02-10-18 terminal 1 index area terminal 1 index area 1/2 e 1/2 e ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 18 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 12. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 12.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 12.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 19 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 12.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 5 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 3 and 14 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 5 . table 13. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 14. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 20 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 13. abbreviations msl: moisture sensitivity level fig 5. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 15. abbreviations acronym description cdm charged-device model cec consumer electronics control ddc data display channel dvi digital visual interface emi electromagnet ic interference esd electrostatic discharge hbm human body model hdmi high-definition multimedia interface hpd hot plug detect i 2 c-bus inter-ic bus i/o input/output nmos negative-channel metal-oxide semiconductor tmds transition minimized differential signaling vesa video electronic st andards association
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 21 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 14. revision history table 16. revision history document id release date data sheet status change notice supersedes ptn3360d v.4 20120629 product data sheet - ptn3360d v.3 modifications: ? phrase changed from ?hdmi v1.4a? to ?hdmi v.1.4b? throughout this data sheet ptn3360d v.3 20120326 product data sheet - ptn3360d v.2 ptn3360d v.2 20101119 product data sheet - ptn3360d v.1 ptn3360d v.1 20100616 product data sheet - -
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 22 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
ptn3360d all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 29 june 2012 23 of 24 nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 licenses 15.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with hdmi technology use of an nxp ic with hdmi technology in equipment that complies with the hdmi standard requires a license from hdmi licensing llc, 1060 e. arques avenue suite 100, sunnyvale ca 94085, usa, e-mail: admin@hdmi.org .
nxp semiconductors ptn3360d hdmi/dvi level shifter supporting 3 gbit/s operation ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 29 june 2012 document identifier: ptn3360d please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 3 2.1 high-speed tmds level shifting . . . . . . . . . . . . 3 2.2 ddc level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 hpd level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 9 7.1 enable and disable features . . . . . . . . . . . . . . . 9 7.1.1 hot plug detect . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1.2 output enable function (oe_n) . . . . . . . . . . . 10 7.1.3 ddc channel enable function (ddc_en). . . . 10 7.1.4 enable/disable truth table . . . . . . . . . . . . . . . . 11 7.2 analog current reference . . . . . . . . . . . . . . . . 12 7.3 equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4 backdrive current protection . . . . . . . . . . . . . . 12 7.5 active ddc buffer with rise time accelerator . 12 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 9 recommended operating conditions. . . . . . . 13 9.1 current consumption . . . . . . . . . . . . . . . . . . . 13 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.1 differential inputs . . . . . . . . . . . . . . . . . . . . . . 14 10.2 differential outputs . . . . . . . . . . . . . . . . . . . . . 14 10.3 hpd_sink input, hpd_source output . . . . 15 10.4 oe_n, ddc_en inputs. . . . . . . . . . . . . . . . . . 15 10.5 ddc characteristics . . . . . . . . . . . . . . . . . . . . 16 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 12 soldering of smd packages . . . . . . . . . . . . . . 18 12.1 introduction to soldering . . . . . . . . . . . . . . . . . 18 12.2 wave and reflow soldering . . . . . . . . . . . . . . . 18 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 12.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 22 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 15.5 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16 contact information . . . . . . . . . . . . . . . . . . . . 23 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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